These devices provide two monolithic independent timing circuits of the NE555 SA555 SE555 or SE555C type in each package.
These circuits can be operated in the astable or monostable mode with external resistor-capacitor timing control.
The basic timing provided by the RC time constant may be actively controlled by modulating the bias of the control voltage input.
The threshold and trigger levels are normally two-thirds and one-third respectively of VCC.
These levels can be altered by use of the control voltage terminal.
When the trigger input falls below trigger level the flip-flop is set and the output goes high.
If the trigger input falls below trigger level the flip-flop is set and the output goes high. I
f the trigger input is above the trigger level and the threshold input is above the threshold level the flip-flop is reset and the output is low.
The reset input can override all other inputs and can be used to initiate a new timing cycle.
When the reset input goes low the flip-flop is reset and the output goes low.
Whenever the output is low a low-impedance path is provided between the discharge terminal and ground.